Low-Power Variation-Tolerant Design in Nanometer Silicon
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Low-Power Variation-Tolerant Design in Nanometer Silicon Edited by: Swarup Bhunia Saibal Mukhopadhyay Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. Coverage includes logic and memory design, modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. Introduces readers to some of the most important challenges in lowpower and variationtolerant IC design in nanoscale technologies; Presents a holistic view of LowPower VariationTolerant Design, at different levels of design abstraction, starting from device to circuit, architecture and system; Offers comprehensive coverage of modeling, analysis and design methodology for low power and variationtolerant logic circuits, memory and systems, microarchitecture, DSP, mixedsignal and FPGAs, including current industrial practices, technology scaling trends, and emerging challenges; Describes in detail modeling and analysis of different variation effects (dietodie and withindie, process and temporal) on lowpower designs; Includes coverage of ultra low-power and robust sub-threshold design.
