Beschreibung
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this work a process variation tolerant wide fan-in dynamic OR gate with two new keeper designs is proposed which are capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay.
Autorenporträt
Vikas Mahor, received the B.Tech. degree in electronics engineering from the Rajeev Gandhi Technical University, Bhopal, in 2007. In July 2012, he has been awarded with an M. Tech. degree in VLSI Design from Indian Institute of Information Technology and Management (IIITM), Gwalior. Currently he is working towards his Ph.D. from IIITM, Gwalior.
Herstellerkennzeichnung:
OmniScriptum SRL
Str. Armeneasca 28/1, office 1
2012 Chisinau
MD
E-Mail: info@omniscriptum.com
