Low-Power High-Speed ADCs for Nanometer CMOS Integration

Lieferzeit: Lieferbar innerhalb 14 Tagen

106,99 €

inkl. 7 % MwSt. zzgl. Versandkosten

Analog Circuits and Signal Processing

ISBN: 9048178851
ISBN 13: 9789048178858
Autor: Cao, Zhiheng/Yan, Shouli
Verlag: Springer Verlag GmbH
Umfang: xiii, 95 S.
Erscheinungsdatum: 22.11.2010
Auflage: 1/2008
Produktform: Kartoniert
Einband: KT

This text is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes.

Artikelnummer: 955020 Kategorie:

Beschreibung

InhaltsangabePreface. List of Tables. List of Figures. 1. Introduction. 1 Motivations. 2 A Review of Existing ADC Architectures. 2. A 52mW 10b 210MS/s Two-Step ADC for Digital IF Receivers in 130nm CMOS. 1 Background. 2 Architecture and Circuits. 3 Experimental Results. 4 Summary. 3. A 32mW 1.25GS/s 6b 2b/Step SAR ADC in 130nm Digital CMOS 47. 1 Background. 2 Architecture. 3 Enabling Circuits. 4 Testing Issues. 5 Experimental Results. 6 Performance Summary and Comparison. 7 Summary. 4. A 0.4psRMSJitter 13GHz Clock Multiplier PLL Using PhaseNoise Preamplification. 1 Introduction. 2 PhaseLock Loop (PLL). 3 VCO and Clock Buffers. 4 Experimental Results. 5 Summary. 5. Conclusions and Future Directions. References. About the Authors.

Inhaltsverzeichnis

Preface. List of Tables. List of Figures. 1. Introduction. 1 Motivations. 2 A Review of Existing ADC Architectures. 2. A 52mW 10b 210MS/s Two-Step ADC for Digital IF Receivers in 130nm CMOS. 1 Background. 2 Architecture and Circuits. 3 Experimental Results. 4 Summary. 3. A 32mW 1.25GS/s 6b 2b/Step SAR ADC in 130nm Digital CMOS 47. 1 Background. 2 Architecture. 3 Enabling Circuits.4 Testing Issues. 5 Experimental Results. 6 Performance Summary and Comparison. 7 Summary. 4. A 0.4ps-RMS-Jitter 1-3GHz Clock Multiplier PLL Using Phase-Noise Preamplification. 1 Introduction. 2 Phase-Lock Loop (PLL). 3 VCO and Clock Buffers. 4 Experimental Results. 5 Summary. 5. Conclusions and Future Directions. References. About the Authors.

Das könnte Ihnen auch gefallen …