Produktbild: Low Power Networks-on-Chip

Low Power Networks-on-Chip

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106,99 €

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ISBN: 1489994378
ISBN 13: 9781489994370
Herausgeber: Cristina Silvano/Marcello Lajolo/Gianluca Palermo
Verlag: Springer Verlag GmbH
Umfang: xix, 287 S.
Erscheinungsdatum: 20.11.2014
Auflage: 1/2014
Produktform: Kartoniert
Einband: Kartoniert

Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues still represent one of the limiting factors in integrating multi- and many-cores on a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networksonchip based architectures; Applies stateoftheart, lowpower design techniques to the design of NetworksonChip, to demonstrate methodology for design of highspeed, lowpower interconnect; Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.

Artikelnummer: 7806724 Kategorie:

Beschreibung

In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.

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