Produktbild: Error Control for Network-on-Chip Links

Error Control for Network-on-Chip Links

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117,69 €

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ISBN: 1489986332
ISBN 13: 9781489986337
Autor: Fu, Bo/Ampadu, Paul
Verlag: Springer Verlag GmbH
Umfang: xi, 151 S.
Erscheinungsdatum: 20.10.2014
Auflage: 1/2014
Produktform: Kartoniert
Einband: Kartoniert

As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed to address the reliability problem of on-chip communications. This book focuses on the use of error control codes (ECCs) to improve on-chip interconnect reliability. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance. – Provides a detailed background on the state of error control methods for on-chip interconnects; Describes the use of more complex concatenated codes such as Hamming Product Codes with TypeII HARQ, while emphasizing integration techniques for onchip interconnect links; Examines energyefficient techniques for integrating multiple error control methods in onchip interconnects; Introduces various design techniques to tradeoff the reliability and energy consumption of onchip interconnects, including implementation of low link swing voltage and dynamic voltage scaling with error control codes, combination of Hamming product codes with typeII hybrid ARQ, and configurable error control codes implementation.  

Artikelnummer: 7804409 Kategorie:

Beschreibung

This book provides readers with a comprehensive review of the state of the art in error control for Network on Chip (NOC) links.  Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance.

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