Beschreibung
In recent years, need of low power testing has become progressively more important in electronic systems, where circuit testing need to be performed periodically. The power dissipation through the testing mode is double with respect to normal operation mode. The higher power consumption may leads to many problems such as difficulty in design, failure to perform intended function, reduction in useful life period and performance yield. A proposed solution to the above mention problems include keeping minimal switching activity (SA) during testing and the high fault coverage (FC) that efficiently reduces defect level of ICs.
Autorenporträt
Dr Sabir Hussain is Associate Professor in Department of Electronics and Communication Engineering of Muffakham Jah College of Engineering and Technology Osmania University Hyderabad Telangana India. He has 13 years of teaching and research experience. He published research articles in international conferences and Journals.
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