Beschreibung
Nowadays in VLSI, the technology size, power, and speed are the main constraints to design any circuits. In normal multipliers, delay will be more and the number of computations also will be more. Because of that speed of the circuits designed with the normal multipliers will be low and it will consume more power. This book describes Multiply and Accumulate Unit using Vedic Multiplier and DKG reversible logic gates. The Vedic Multiplier is designed by using Urdhava Triyagbhayam sutra and the adder design is done by using reversible logic to perform high speed operations. Reversible logic gates are also the essential constraint for the promising field of Quantum computing. The Urdhava Triyagbhayam multiplier is used for the multiplication function to reduce partial products in the multiplication process and to get high concert and less area. The reversible logic is used to get less power. The MAC is designed using Verilog code, simulation, synthesis is done in both RTL compiler using Xilinx and implemented on Spartan 3e FPGA Board.
Autorenporträt
Mr. P. Siva Nagendra Reddy was born in Anantapur District, A.P.,India.He obtained Masters Degree in VLSI System Design from JNTU Anantapur in 2013.Mr. Siva is working as an Assistant Professor in the Department of ECE, Kuppam Engineering College,JNTU,Anantapur. His research interests are VLSI,IOTs and Embedded Systems.He is a member of ISTE and IEI.
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