FPGA based implementation of self timed FIR filter

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45,90 

Methodology, Modeling, Implementation

ISBN: 3659842702
ISBN 13: 9783659842702
Autor: C P, Jithesh
Verlag: Scholars‘ Press
Umfang: 56 S.
Erscheinungsdatum: 06.10.2016
Auflage: 1/2016
Format: 0.4 x 22 x 15
Gewicht: 102 g
Produktform: Kartoniert
Einband: Kartoniert
Artikelnummer: 9962690 Kategorie:

Beschreibung

This book proposes a methodology for implementing digital circuits and systems using asynchronous scheme called as self-timing. A methodology which results in average case performance vs. worst-case performance of the digital system without the global clocking overhead. The primary objective of the book is to give the readers an overview of the self-timing methodology, how to build smaller to medium scale digital circuits, modeling for HDL simulation and fast prototyping on Field Programmable Gate Arrays. This book is suggested to readers who are doing their master's degree in electronics engineering with specialization in VLSI/Embedded Systems.

Autorenporträt

Jithesh C. P., working as Assistant Professor, Department of Electronics Engineering, Government Engineering College, Kozhikode, India. He has acquired B.Tech, ECE (Calicut University) in 2002, M.Tech, VLSI System (NIT Trichy) in 2005. He has around 5 years semiconductor industry experience and more than 5 years of teaching experience.

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