Beschreibung
This is an approach to Design of Energy Efficient Manchester Decoder Using State Machine Implementation on FPGA that consumes low amount of power. This is done by varying various aspects such as ambient temperature, IOs standards, capacitance, frequency and FPGA change to different level and checking corresponding amount of energy consumed. Manchester coding technique is a digital coding technique in which all the bits of the binary data are arranged in a particular sequence. The Encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. The Decoder recognizes the sync pulse and identifies it as well as decoding the data bits and checking parity. This integrated circuit is fully guaranteed to support the 1MHz data rate of MlL-STD-1553 over both temperature and voltage. This report addresses the design of a Manchester decoder using State Machines. The Manchester Decoder are the Front End logics of MIL-STD-1553B protocol, which is a standard Avionics Bus. The decoder is represented using state machines, which is a method generally used in the design of Synchronous Systems as against the conventional design methodology of representing the design.
Autorenporträt
Sujeet Kumar Pandey is a director of Gyancity Research Lab Private Limited, Motihari, India. He has completed his Master of Technology in Aeronautical Engineering from Jain University, Bangalore. He is an associate member of Aeronautical Society of India, New Delhi. He has the research collaboration with researchers from Italy, Malaysia, Denmark.
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