Beschreibung
Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design discusses new approaches to better timing-closure and manufacturability of DSM Integrated Circuits. The key idea presented is the use of regular circuit and interconnect structures such that area/delay can be predicted with high accuracy. The co-design of structures and algorithms allows great opportunities for achieving better final results, thus closing the gap between IC and CAD designers. The regularities also provide simpler and possibly better manufacturability. In this book we present not only algorithms for solving particular sub-problems but also systematic ways of organizing different algorithms in a flow to solve the design problem as a whole. A timing-driven chip design flow is developed based on the new structures and their design algorithms, which produces faster chips in a shorter time.
Autorenporträt
InhaltsangabePreface Acknowledgements 1: Introduction 1.1. The Deep Sub-Micron IC Design 1.2. Outline 2: Preliminaries 2.1. Overview 2.2. CMOS Technology 2.2.1. Transistors 2.2.2. Gates 2.2.3. CMOS storage components 2.2.4. Interconnections 2.3. IC Design and System-On-a-Chip 2.3.1. System and constraints 2.3.2. Design styles 2.3.3. System-On-a-Chip 2.4. Design Automation 2.5. Challenges in the Deep Sub-Micron Era 2.5.1. The Deep Sub-Micron challenges 2.5.2. Dealing with the DSM challenges 2.6. Summary 3: Circuit Structures 3.1.Overview 3.2. Standard-cell 3.2.1. The structure and usage of the standard-cell 3.2.2. Existing design methodology for the standard-cell 3.2.3. An Integrated Standard-cell Physical Design 3.2.4. Summary of the standard-cell structure 3.3. PLA 3.4. Network of PLAs 3.5. River PLA 3.5.1. Overview 3.5.2. The structure of the RPLA 3.5.3. The design methodology 3.5.4. Experimental results 3.5.5. Summary 3.6. Whirlpool PLA 3.6.1. The circuit structure of the WPLA 3.6.2. Doppio-ESPRESSO 3.6.3. Experimental results 3.6.4. Summary 3.7. Checkerboard 3.7.1. The structure of Checkerboard and its dynamic operation 3.7.2. The algorithm 3.7.3. Experimental results 3.7.4. Summary and discussion 3.8. Comparison of the Structures 4: Block Level Placement and Routing 4.1. Overview 4.2. The Fishbone Scheme 4.2.1. An overview of the Fishbone scheme 4.2.2. The basics of the Fishbone routing 4.2.3. Interval packing for branches and trunks 4.2.4. I/Opins 4.2.5. The Fishbone placement and routing flow 4.2.6. Experimental results 4.2.7. Summary of the Fishbone scheme 4.3. Fishbone with Buffer Insertion 4.3.1. The buffers 4.3.2. Buffer insertion 4.3.3. The Fishbone-B physical design flow 4.3.4. Experimental results 4.3.5. Summary of the Fishbone-B 4.4. Summary 5: The Design Flow 5.1. Overview 5.2. Basics of the Design Flow 5.2.1. Modules and paths 5.2.2. Timing constraints for the modules 5.2.3. The relation of module area and constraint 5.2.4. The problems and possible solutions 5.3. The Physical Synthesis Flow 5.4. The Module Based Design Flow 5.4.1. Overview 5.4.2. The version of soft module 5.4.3. The physical design stage 5.4.4. Summary of the Module-Based design flow 5.5. Comparison of the Two Flows 5.5. Generation of the testing examples 5.5.2. The 0.18-micron technology 5.5.3 The testing circuits 5.5.4. The comparison 5.5.5. Case study: A l 5.6. Summary 6: Conclusion Bibliography Index
