Beschreibung
InhaltsangabeIntroduction; T.H. Meng, S. Malik. Self-Timed Logic using Current-Sensing Completion Detection (CSCD); M.E. Dean, D.L. Dill, M. Horowitz. Performance of Iterative Computation in Self-Timed Rings; T.E. Williams. High Level Optimizations in Compiling Process Descriptions to Asynchronous Circuits; G. Gapalakrishnan, V. Akella. Designing Self-Timed Systems using Concurrent Programs; E. Brunvand. Synthesis of Hazard-Free Control Circuits from Asynchronous Finite State Machines Specifications; Tam-Anh Chu. Specification, Synthesis and Verification of Hazard-Free Asynchronous Circuits; C.W. Moon, P.R. Stephan, R.K. Brayton. A Generalized State Assignment Theory for Transformations on Signal Transition Graphs; P. Vanbekbergen, B. Lin, G. Goossens, H. De Man. Specification and Analysis of Self-Timed Circuits; M.A. Kishinevsky, A.Yu. Kondratyev, A.R. Taubin. Linear Programming for Hazard Elimination in Asynchronous Circuits; L. Lavagno, N. Shenoy, A. Sangiovanni-Vincentelli. Verification of Asynchronous Interface Circuits with Bounded Wire Delays; S. Devadas, K. Keutzer, S. Malik, A. Wang. Subject Index.
Inhaltsverzeichnis
Introduction; T.H. Meng, S. Malik. Self-Timed Logic using Current-Sensing Completion Detection (CSCD); M.E. Dean, D.L. Dill, M. Horowitz. Performance of Iterative Computation in Self-Timed Rings; T.E. Williams. High Level Optimizations in Compiling Process Descriptions to Asynchronous Circuits; G. Gapalakrishnan, V. Akella. Designing Self-Timed Systems using Concurrent Programs; E. Brunvand. Synthesis of Hazard-Free Control Circuits from Asynchronous Finite State Machines Specifications; Tam-Anh Chu. Specification, Synthesis and Verification of Hazard-Free Asynchronous Circuits; C.W. Moon, P.R. Stephan, R.K. Brayton. A Generalized State Assignment Theory for Transformations on Signal Transition Graphs; P. Vanbekbergen, B. Lin, G. Goossens, H. De Man. Specification and Analysis of Self-Timed Circuits; M.A. Kishinevsky, A.Yu. Kondratyev, A.R. Taubin. Linear Programming for Hazard Elimination in Asynchronous Circuits; L. Lavagno, N. Shenoy, A. Sangiovanni-Vincentelli. Verification of Asynchronous Interface Circuits with Bounded Wire Delays; S. Devadas, K. Keutzer, S. Malik, A. Wang. Subject Index.
