Beschreibung
We propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on-capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs.
Autorenporträt
A. Raghavaraju received his M.Tech from ANNA University Chennai and B.Tech from JNTU Hyderabad. Currently he is pursuing PhD from K. Lakshmaiah Education Foundation, India. Presently he is working as Assoc. Prof. in the Department of E.C.E., Chebrolu Engg. College. He published several works in international journals and scopus indexed journals.
