Beschreibung
The development of computing machines found great success in the last decades. But the ongoing miniaturization of integrated circuits will reach its limits in the near future. Shrinking transistor sizes and power dissipation are the major barriers in the development of smaller and more powerful circuits. Reversible logic p- vides an alternative that may overcome many of these problems in the future. For low-power design, reversible logic offers signi?cant advantages since zero power dissipation will only be possible if computation is reversible. Furthermore, quantum computation pro?ts from enhancements in this area, because every quantum circuit is inherently reversible and thus requires reversible descriptions. However, since reversible logic is subject to certain restrictions (e.g. fanout and feedback are not directly allowed), the design of reversible circuits signi?cantly differs from the design of traditional circuits. Nearly all steps in the design ?ow (like synthesis, veri?cation, or debugging) must be redeveloped so that they become applicable to reversible circuits as well. But research in reversible logic is still at the beginning. No continuous design ?ow exists so far. Inthisbook,contributionstoadesign?owforreversiblelogicarepresented.This includes advanced methods for synthesis, optimization, veri?cation, and debugging.
Inhaltsverzeichnis
1. Introduction. 2. Preliminaries. 2.1. Background. 2.2. Decision Diagrams. 2.3. Satisfiability Solvers. 3. Synthesis of Reversible Logic. 3.1. Current Synthesis Steps . 3.2. BDD-based Synthesis. 3.3. SyReC: A Reversible Hardware Language. 3.4. Summary and Future Work. 4. Exact Synthesis of Reversible Logic. 4.1. Main Flow. 4.2. SAT-based Exact Synthesis. 4.3. Improved Exact Synthesis. 4.4. Summary and Future Work. 5. Embedding of Irreversible Functions. 5.1. Embedding Problem. 5.2. Don¿t Care Assignment. 5.3. Synthesis with Output Permutation. 5.4. Summary and Future Work. 6. Optimization. 6.1. Adding Lines to Reduce Circuit Cost. 6.2. Reducing the Number of Circuit Lines. 6.3. Optimizing Circuits for Linear Nearest Neighbor Architectures. 6.4. Summary and Future Work. 7. Formal Verii¬cation and Debugging. 7.1. Equivalence Checking. 7.2. Automated Debugging and Fixing. 7.3. Summary and Future Work. 8. Summary and Conclusions. References. Index.
