Power and Area Optimization in NoC by using Tailor Made Partitioning

Lieferzeit: Lieferbar innerhalb 14 Tagen

49,90 

ISBN: 3659908029
ISBN 13: 9783659908026
Autor: Lit, Asrani/Sebastian Itap, Charles Luan
Verlag: LAP LAMBERT Academic Publishing
Umfang: 92 S.
Erscheinungsdatum: 15.07.2016
Auflage: 1/2016
Format: 0.7 x 22 x 15
Gewicht: 155 g
Produktform: Kartoniert
Einband: Kartoniert
Artikelnummer: 9655146 Kategorie:

Beschreibung

NoC became a new paradigm to replace the SoC since the existing bus based system unable to accommodate the complexity of the SoC. A huge number of components were involved in the on-chip design. Each of these components needs to communicate with each other and carry their own function that will affect the scalability and the testability of the SoC in general. This project analyzes the main sources of power consumption in NoC based systems. Analytical power models of global interconnection links are studied at different levels of abstraction. Additionally, power measurement experiments are performed for different types of n-level network with related to die area of NoC.

Autorenporträt

Muhamad Qaedi Edanan is a Bachelor in Electronic Engineering (Computer) from Universiti Malaysia Sarawak (UNIMAS). Asrani Lit is a Research Scientist at Department of Electrical and Electronic in UNIMAS.

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