Beschreibung
Nanoscaled CMOS technology brings various critical challenges and reliability issues such as short channel effects, variations in I-V characteristics, reduced gate control, larger process variations and high leakage current etc. To overcome these difficulties, scientists and researchers are working towards new alternatives of conventional CMOS process. In digital electronic world, delay and power consumption improvement are the most important performance parameters of a circuit. To reach this goal, we can reduce scaling of the feature size. But scaling brings challenges. In complementary metal oxide semiconductor (CMOS) technology, reducing the length of channel to below about 65nm leads to critical problems and challenges such as decreasing gate control, short channel effect, high power density, high sensitivity to process variation and exponential leakage current increment. For this reasons reducing the transistors size finally will stop at a point, leading to taking advantage of new technologies that do not have above problems may be felt.
Autorenporträt
Saurabh Mitra has over 9 years of experience in teaching and learning. More than 25 of his papers were published in national and international journals. He also received two international awards for his researches and innovations.
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BoD - Books on Demand
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