Beschreibung
InhaltsangabeIntroduction. About the Editors. Acknowledgements. Architectures. 1. Extra-dimensional island-style FPGAs. 2. A tightly coupled VLIW/reconfigurable matrix and its modulo scheduling technique. 3. Stream-based XPP Architectures in adaptive System-on-Chip Integration. 4. Core-based architecture for data transfer control in SOC design. 5. Customizable and reduced hardware motion estimation processors. Methodologies and Tools. 6. Enabling run-time task relocation on reconfigurable systems. 7. A unified co-design environment for the UltraSonic reconfigurable computer. 8. Mapping applications to a coarse grain reconfigurable system. 9. Compilation and temporal partitioning for a coarse-grain reconfigurable architecture. 10. Run-time defragmentation for dynamically reconfigurable hardware. 11. Virtual hardware byte code as a design platform for reconfigurable embedded systems. 12. A low energy data management for multi-context reconfigurable architectures. 13. Dynamic and partial reconfiguration in FPGA SoCs: requirements tools and a case study. Applications. 14. Design flow for a reconfigurable processor. 15. IPsec-Protected Transport of HDTV over IP. 16. Fast, large-scale string matching for a 10 Gbps FPGA-based network intrusion detection system. 17. Architecture and FPGA implementation of a digit-serial RSA Processor. 18. Division in GF(p) for application in elliptic curve cryptosystems on field programmable logic. 19. A New Arithmetic Unit in GF(2m) for Reconfigurable Hardware Implementation. 20. Performance Analysis of SHACAL-1 Encryption Hardware Architectures. 21. Security aspects of FPGAs in cryptographic applications. 22. Bioinspired stimulus encoder for cortical visual neuroprostheses. 23. A Smith-Waterman Systolic Cell. 24. The effects of polynomial degrees.
Inhaltsverzeichnis
Introduction. About the Editors. Acknowledgements. Architectures. 1. Extra-dimensional island-style FPGAs. 2. A tightly coupled VLIW/reconfigurable matrix and its modulo scheduling technique. 3. Stream-based XPP Architectures in adaptive System-on-Chip Integration. 4. Core-based architecture for data transfer control in SOC design. 5. Customizable and reduced hardware motion estimation processors. Methodologies and Tools. 6. Enabling run-time task relocation on reconfigurable systems. 7. A unified co-design environment for the UltraSonic reconfigurable computer. 8. Mapping applications to a coarse grain reconfigurable system. 9. Compilation and temporal partitioning for a coarse-grain reconfigurable architecture. 10. Run-time defragmentation for dynamically reconfigurable hardware. 11. Virtual hardware byte code as a design platform for reconfigurable embedded systems. 12. A low energy data management for multi-context reconfigurable architectures. 13. Dynamic and partial reconfiguration in FPGA SoCs: requirements tools and a case study. Applications. 14. Design flow for a reconfigurable processor. 15. IPsec-Protected Transport of HDTV over IP. 16. Fast, large-scale string matching for a 10 Gbps FPGA-based network intrusion detection system. 17. Architecture and FPGA implementation of a digit-serial RSA Processor. 18. Division in GF(p) for application in elliptic curve cryptosystems on field programmable logic. 19. A New Arithmetic Unit in GF(2m) for Reconfigurable Hardware Implementation. 20. Performance Analysis of SHACAL-1 Encryption Hardware Architectures. 21. Security aspects of FPGAs in cryptographic applications. 22. Bioinspired stimulus encoder for cortical visual neuroprostheses. 23. A Smith-Waterman Systolic Cell. 24. The effects of polynomial degrees.