Beschreibung
This book presents a hardware architecture and the associated design methodology to generate an application specific processing element array. The novel design methodology reverses the traditional design concept of mapping an application on a fixed array with an innovative concept where the hardware array layout is generated as per the requirements of the targeted application. The architecture provides an optimal mix of adaptivity, performance and programability.
Autorenporträt
Sunil received Ph.D. degree from the University of Queensland, Australia and B.E. degree from the Pune University, India. He has extensive experience in the field of ASIC/FPGA based system design. He has consulted as an FPGA expert for a number of companies.
