High Performance Multi-Channel High-Speed I/O Circuits

Lieferzeit: Lieferbar innerhalb 14 Tagen

106,99 

Analog Circuits and Signal Processing

ISBN: 1493954229
ISBN 13: 9781493954223
Autor: Oh, Taehyoun/Harjani, Ramesh
Verlag: Springer Verlag GmbH
Umfang: x, 89 S., 20 s/w Illustr., 44 farbige Illustr., 89 p. 64 illus., 44 illus. in color.
Erscheinungsdatum: 23.08.2016
Auflage: 1/2014
Produktform: Kartoniert
Einband: KT

This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds.  This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures. ·         Describes technology and design ideas for power-efficient crosstalk cancellation in multi-channel high-speed I/O circuits;·         Includes critical background knowledge related to channel ISI equalization circuits;·         Provides crosstalk cancellation circuit methods that can be adapted efficiently to currently used equalization circuits in high-speed I/O receivers; key crosstalk cancellation blocks can be merged easily with automatic gain control (AGC) circuits in current I/O systems.

Artikelnummer: 9730775 Kategorie:

Beschreibung

This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures.

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