Beschreibung
InhaltsangabeIntroduction; E.G. Friedman. Clock Skew Optimization for Peak Current Reduction; L. Benini, et al. Clocking Optimization and Distribution in Digital Systems with Scheduled Skews; Hong-Yean Hsieh, et al. Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations; J.L. Neves, E.G. Friedman. Useful-Skew Clock Routing with Gate Sizing for Low Power Design; J.G. Xi, W. W.-M. Dai. Clock Distribution Methodology for PowerPCTM Microprocessors; S. Ganguly, et al. Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology; D.J. Hathaway, et al. Practical Bounded-Skew Clock Routing; A. Kahng, C.-W. A. Tsao. A Clock Methodology for High-Performance Microprocessors; K.M. Carrig, et al. Optical Clock Distribution in Electronic Systems; S.K. Tewksbury, L.A. Hornak. Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits; K. Gaj, et al.
Autorenporträt
InhaltsangabeIntroduction; E.G. Friedman. Clock Skew Optimization for Peak Current Reduction; L. Benini, et al. Clocking Optimization and Distribution in Digital Systems with Scheduled Skews; Hong-Yean Hsieh, et al. Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations; J.L. Neves, E.G. Friedman. Useful-Skew Clock Routing with Gate Sizing for Low Power Design; J.G. Xi, W. W.-M. Dai. Clock Distribution Methodology for PowerPCTM Microprocessors; S. Ganguly, et al. Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology; D.J. Hathaway, et al. Practical Bounded-Skew Clock Routing; A. Kahng, C.-W. A. Tsao. A Clock Methodology for High-Performance Microprocessors; K.M. Carrig, et al. Optical Clock Distribution in Electronic Systems; S.K. Tewksbury, L.A. Hornak. Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits; K. Gaj, et al.
