Beschreibung
In this system, there is presented a new class of hybrid AHt-MPSoC architecture in which hardware accelerators are shared between processors in such a way that to reduce system cost and increase performance. A novel hybrid memory scheme is proposed by this scheme is assessed through extensive simulation to show significant improvements in performance. Hybrid Asymmetric heterogeneous MPSoC architecture consists of a Static Random Access Memory (SRAM) and an embedded Dynamic Random Access Memory (eDRAM) cell in association to Hardware Accelerator (HWA) shared methodology to determine the common computational tasks in between the concurrent tasks of application. An experimental result shows that the proposed hybrid AHt-MPSoC system power consumption reduced from the existing system and their area/performance tradeoffs evaluated very quickly.
Autorenporträt
Dr. R. Arun Prasath, Professor in the Department of ECE at Siddhartha Institute of Technology & Science,Telangana. Received his Ph.D in ICE from Anna University, Chennai. He possess 10 plus years of experience in teaching as well as in research. His research interest includes VLSI Signal Processing, Lowpower VLSI & WIreless sensor Network.
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