Beschreibung
The main objective of this book is to provide new low power, low area and low power delay product solution for Very Large Scale Integration (VLSI) designers. At circuit level, Hybrid PTL/CMOS logic style gives best results over CMOS only and PTL only. A fine cost-performance ratio comparator design based on modified 1s complement principle and conditional sum adder scheme using Hybrid PTL/CMOS logic style has been proposed in this report and the proposed design has small power dissipation, low power delay product and less area over various parameter ranges. Simulations are based on BSIM 3V3 90nm CMOS technology. It shows an 8-bit comparator of the proposed architecture only needs 154 transistors.
Autorenporträt
Ms. Geetanjali Sharma received her Master's degree in VLSI Design and B.Tech degree in Electronics and Communication Engg. from Rajasthan University,India.She is currently working as an Assistant Professor with MSIT, Indraprastha University, New Delhi in Electronics Department.Her research interests are Low Power and Digital VLSI Design.
Herstellerkennzeichnung:
BoD - Books on Demand
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E-Mail: info@bod.de
