Beschreibung
This book describes a tool suite, VEasy, which was developed specifically for aiding the process of teaching Functional Verification. VEasy contains four main modules that perform linting, simulation, coverage collection/analysis and testcase generation, which are considered key challenges to achieve verification success. Each of those modules is commented in details throughout the chapters. All the modules are integrated and built on top of a Graphical User Interface. This framework enables the testcase automation methodology which is based on layers, where one is capable of creating complex test scenarios using drag-and-drop operations. Whenever possible examples are given using simple Verilog designs. The capabilities of the tool and its performance are also compared with some commercial and academic functional verification tools.
Autorenporträt
Samuel is currently a researcher at Télécom ParisTech, Paris, France. He received the titles of Computer Eng. and Master in Microelectronics in 2008 and 2011, respectively, from Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil. His main research interests are circuit design/verification, fault tolerance and single-event effects.
