RTM Kernel Implementation on FPGA using High Level Synthesis Tool

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39,90 €

ISBN: 365955765X
ISBN 13: 9783659557651
Autor: Hussain, Tassadaq/Haider, Amna
Verlag: LAP LAMBERT Academic Publishing
Umfang: 56 S.
Erscheinungsdatum: 27.07.2014
Auflage: 1/2014
Format: 0.4 x 22 x 15
Gewicht: 102 g
Produktform: Kartoniert
Einband: Kartoniert
Artikelnummer: 7021576 Kategorie:

Beschreibung

The efficient data management is a key to the performance for many High Performance Computing (HPC) applications. The programmable devices normally support efficient utilization of data by providing a fixed architecture of caches or scratch pad memories. These caches or scratch pad memories are designed on the basis of few heuristics that are generic enough to provide varying degree of performance enhancement for various applications. However, the performance for applications having complex data accesses can still be improved by providing more customized memory layouts for those applications.

Autorenporträt

Tassadaq is a Ph.D. researcher at the Universitat Politècnica de Catalunya, BarcelonaTech. For the period of his Ph.D., he is working as a research student in the Computer Science group at the Microsoft Barcelona Supercomputing Center Mircorsoft Research Center (BSCMRC).

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