Invasive Tightly Coupled Processor Arrays

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Computer Architecture and Design Methodologies

ISBN: 9811093172
ISBN 13: 9789811093173
Autor: LARI, VAHID
Verlag: Springer Verlag GmbH
Umfang: xxiii, 149 S., 3 s/w Illustr., 49 farbige Illustr., 149 p. 52 illus., 49 illus. in color.
Erscheinungsdatum: 07.06.2018
Auflage: 1/2016
Produktform: Kartoniert
Einband: KT

This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desired number of processing elements (PEs) or region within a TCPA exclusively for an application according to performance requirements. It not only presents models for implementing invasion strategies in hardware, but also proposes two distinct design flavors for dedicated hardware components to support invasion control on TCPAs.

Artikelnummer: 5451863 Kategorie:

Beschreibung

Autorenporträt

Vahid Lari is a researcher at the Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg (FAU), since 2008. He defended his PhD degree on the topic of "Invasive Tightly Coupled Processor Arrays" in November 2015. He received his bachelor degree in computer engineering in 2005 from University of Isfahan, Iran, and master degree in computer architectures in 2007 from Sharif University of Technology, Iran. His main research interests include fault tolerance, programmable hardware accelerators, the design of massively parallel architectures and system level performance evaluation.

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