Beschreibung
The increasing popularity of the Internet stimulates an explosive growth of the data transmitted on the Internet as well as the dramatic increase of the transmission speeds. As a result the TCP/IP processing has become a bottleneck. Traditional software based TCP/IP processing on general purpose processors (GPPs) is no longer able to keep pace with network wire speeds. Consequently, there is an urgent need to design performance-critical TCP/IP functions as special units to accelerate the processing speeds and to offload the processing tasks from GPPs. Such functional units performing micro-level functions can be implemented on field - programmable gate arrays (FPGAs.) FPGAs as programmable hardware devices are particularly suitable to encompass both high processing speeds and flexibility to meet the quickly changing Internet. A challenge in designing the TCP/IP function is that the demand for advanced services requires the network devices to support a wide range of application and protocols; however this application and protocols are constantly evolving.
Autorenporträt
Mr. Mahesh B Dembrani has obtained his Master of Engineering in Digital Electronics from Amravati University, Amravati. He has 10 Years of teaching and research experience. Presently he is working on Signal Processing with special focus on medical and communication applications.
