Beschreibung
This book is focused to provide significant improvements over the existing designs reported in last decade. The design objective is to minimize the jitter and phase noise which can be integrated with high speed ASIC design. After carrying out thorough literature survey, simulations and analysis, modifications are done to bring novelty in proposed digital phase locked loop design. The modified TSPC Logic based D flip flop is designed to build phase frequency detector to reduce dead zone. In addition to that it provides good adaptability. To improve the current matching characteristics, current mode differential charge pump design is used. This design provides full swing in turn clock signal can handle full swing. LC based oscillator is used for Sub Harmonic Injection locking concept to increase the clock speed. It can also provide wide tuning range. Added Delay Locked Loop block to achieve desired range with improved noise and jitter performance.
Autorenporträt
Dr. Nilesh D. Patel has done his Ph. D. from Nirma University, Ahmedabad in VLSI Design. He has more than 15 years of experience in teaching UG & PG students. At present he is working as a Principal at M. L. Institute of Diploma Studies, Bhandu, Gujarat, India. He has published many technical papers in international journals and conferences.
