Beschreibung
The growing number of cores increases the demand for a powerful memory subsystem which leads to enhancement in the size of caches in multicore processors. Caches are responsible for giving processing elements a faster, higher bandwidth local memory to work with. This text presents an analysis to study the impact of cache size on performance of Multi-core processors by varying L1 and L2 cache size on the multicore processor with internal network (MPIN) referenced from NIAGRA architecture. The effect of interconnections on the performance of multicore processors has been analyzed and a novel scalable, on-chip interconnection mechanism (INOC) for multicore processors has been proposed. A full system simulator multi2sim has been used to analyze the performance of different proposed architectures using Splash2 benchmark.
Autorenporträt
Ram Prasad Mohanty is currently pursuing research internship at National University of Singapore and has been a Research Scholar in Computer Science & Engineering (CSE) department of NIT Rourkela, India. His area of interest is Multicore Processor, & High performance computing.
Herstellerkennzeichnung:
OmniScriptum SRL
Str. Armeneasca 28/1, office 1
2012 Chisinau
MD
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