A Novel approach for Fault Tolerant Nano Memory Applications

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35,90 

ISBN: 3659894419
ISBN 13: 9783659894411
Autor: Pavan Kumar, Chinnala
Verlag: LAP LAMBERT Academic Publishing
Umfang: 68 S.
Erscheinungsdatum: 17.06.2016
Auflage: 1/2016
Format: 0.5 x 22 x 15
Gewicht: 119 g
Produktform: Kartoniert
Einband: Kartoniert
Artikelnummer: 9552408 Kategorie:

Beschreibung

NANOTECHNOLOGY provides smaller, faster, and lower energy devices which allow more powerful and compact circuitry; However, these benefits come with a costthe nanoscale devices may be less reliable. Thermal- and shot-noise estimations alone suggest that the transient fault rate of an individual nanoscale device (e.g., transistor or nanowire) may be orders of magnitude higher than todays devices. A failure is said to have occurred in a circuit or system if it deviates from its specified behavior. A fault on the other hand is physical defect which may or may not cause a failure. The failure rate, also known as the hazard rate and defined as number of failures per unit time compared with the number of surviving components. A fault is characterized by its nature, value, extent & duration.

Autorenporträt

Ch Pavan Kumar received B.Tech in ECE & M.Tech in VLSI from Jawaharlal Nehru Technological University Hyderabad, India, Currently; he is pursing the Ph.D. degree in JNTUH, Hyd. Presently working as Assistant Professor, Dept. of ECE, KITS, Warangal. His research includes VLSI design, Ultra Low Power Designs and Sub threshold region modelling.

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